Reprogrammable FPGAs have been available commercially for several years. The best known commercial family of FPGAs are those from Xilinx, Inc. One class of these devices uses Static Random Access Memory (SRAM) cells to hold control bits which control their configurations. Each SRAM cell controls one or more transistors at the configurable points in an FPGA or serves as one or more entries in a lookup table. (The configuration memory cells collectively determine what functions the FPGA will implement.)
The present invention will be described in connection with SRAM FPGAs. The configuration of the FPGA is typically loaded from a non-volatile configuration memory into the SRAM configuration memory cells when power is applied to the system.
Some commercially available SRAM FPGAs have a stream-based interface to the SRAM configuration memory. That is, a stream of data is applied to one or a few pins in the FPGA and shifted in through a shift register to destination SRAM cells to provide a configuration for the whole device or for a subsection of the FPGA. This stream-based interface provides an efficient method of loading the complete device configuration from an external source without any additional overhead circuits such as row and column decoders. In prior art stream-based FPGAs, the locations of the destination SRAM cells are not individually addressable. For some stream based interfaces, in order to make any changes in the configuration, an entire section of the configuration memory must be reloaded.
Other SRAM FPGAs are RAM addressable, and use data and address lines each connected to a separate external pin to access the configuration memory in a way similar to that used to access any random access memory. With an addressable configuration memory, an external processor can perform word-wide read or write operations on the registers of the user's design without having to re-load other parts of the configuration data. In such systems, a small portion of the configuration memory can be changed rapidly, and the remaining configuration memory may remain undisturbed. Thus the configuration memory interface allows high bandwidth (high speed) communication between the processor and the FPGA. Such systems may provide mechanisms for synchronizing computations between the FPGA and a processor outside the FPGA, and provide a mechanism to support dynamic reconfiguration. In dynamic reconfiguration, partial reconfiguration occurs while the remainder of the FPGA is in use. These systems still allow use of conventional design tools to create FPGA configurations for static designs.
Configuration information may be loaded from a variety of sources, for example, from the memory accessed by a microprocessor, from a non-volatile PROM under control of the FPGA itself (see description in Freeman, U.S. Reissue Pat. No. 34,363), or by mapping the FPGA configuration memory into the address space of the microprocessor.
Partial reconfiguration may also occur from within some known FPGAs. Freeman in U.S. Pat. No. 5,343,406 [docket M-936] describes a lookup table FPGA in which the lookup tables which generate combinatorial functions can be loaded both from an externally supplied configuration bit stream and from the interconnect wiring within the FPGA. Thus partial reconfiguration of these FPGA chips can occur. Such FPGA chips are available from Xilinx, Inc. as the XC4000 series FPGA chips.
Several goals are important to consider when designing an FPGA. Since package pins on an FPGA are limited, it is important that loading the configuration information require as few dedicated package pins as possible in order to leave as many pins as possible for user input and output after the FPGA has been configured. (Using certain pins for loading data during configuration and then making them available for another purpose after configuration does not limit the number of pins available for user logic.) Also, the structure of the FPGA should require that as few additional components as possible be added to the board in which the FPGA is to be placed. (One purpose of using an FPGA is to reduce board part count). It is also important to some users that the FPGA configuration structure allow for partial and fast reconfiguration. It is further beneficial for a user to be able to access internal gates and registers during operation. (A system for allowing a user to access internal gates and registers during operation is described in Patent Cooperation Treaty patent application serial No. WO 94/10754 published 11 May 1994 [docket MA-002]).
Present FPGAs attempt to meet these conflicting goals by providing a variety of programming modes (serial bit stream load, parallel bit stream load, loading under control of a microprocessor, etc.). Offering these options requires a relatively complex set of programming logic on the FPGA. Some modes require more pins and others require more programming time. For example, serial mode uses only one data pin whereas parallel mode may require 8 or 16 data pins. But serial mode takes at least 8 or 16 times as long to load the configuration. Not all the pins used during configuration are dedicated to that purpose. However, selecting between these modes has required dedicating a set of pins on the FPGA to selecting the mode.
In present RAM addressable FPGAs some of the pins of the FPGA are dedicated to address lines, data lines, and other control lines for loading the configuration memory, while other pins are dedicated to input and output of user logic. FIG. 1 shows such an FPGA chip and the relationships between external pads, the FPGA user logic structures, and the configuration memory which configures the user logic. It is convenient to visualize the FPGA as formed in first and second stories, a first story holding the configuration information which selects the functions performed by the FPGA, and a second story which performs the function selected by the user. FIG. 1 illustrates the FPGA in this manner. (Physically, the configuration memory and the user logic are formed on the same substrate of an integrated circuit structure. This structure is described in PCT application serial No. WO 94/10754 published May 11, 1994.)
As shown in FIG. 1, some of the pads are for accessing user logic 19 and others are for addressing and loading configuration memory 25. The pad drivers 18 are configured by a user-generated enable signal to determine whether a particular user logic pad 16 is an input pad, an output pad, or unused. Switches such as switch 15 are configured by the underlying configuration memory 25 to transfer signals between the pad drivers 18 and the internal user logic 19. Such internal user logic is discussed in detail by the present inventor in Patent Cooperation Treaty patent application serial No. WO 94/10754 published 11 May 1994. Pads R0 through R3, R/W, CE, CK, RST, C0 through C2. D0 through D7 and their related pins (not shown in FIG. 1) are dedicated to the configuration function. A commercially available device typically has more pads for both configuration and user logic than shown in FIG. 1.
Configuration memory 25 is loaded by addressing a memory cell or memory word as is done in a conventional RAM. Row and column address busses 22 and 27 carry address signals which are decoded by row and column decoders 21 and 26, and connect a selected word of configuration memory 25 to configuration data bus 23 to be read or written. Pads D0 through D7 are coupled to configuration data bus 23.
FIG. 2 shows the relationship between the address and data busses, the row and column decode structures, the eight bit drivers associated with each word, and the data locations in the configuration memory array 25. Such structures are well known in the art. Betty Prince in "Semiconductor Memories" .COPYRGT.1983, 1991 by John Wiley & Sons discusses such structures at pages 149-174.
Also shown in FIG. 1 is memory load control unit 24. Control unit 24 enables row and column decoders 21 and 26 in response to well known clock, chip enable, and reset signals from pads CE, CK and RST respectively. Memory control unit 24, in response to a read/write signal on pad R/W, determines whether pads D0 through D7 will have an input configuration for writing or an output configuration for reading data bus 23.
If the structure of FIG. 1 is to be reconfigured or partially reconfigured during operation, an external device such as a microprocessor addresses portions of the configuration memory and loads new data into those locations.
FIG. 3A shows the relationship between parts of the FPGA user logic of FIG. 1, namely a pad 16, the related pad driver 18, and a switch 15 in the user logic. In FIG. 3A, switch 15, which in FIG. 3A is located at the east edge of the FPGA, sends and receives signals between user logic at the left and the external pad 16 and pin 17 at the right. Lines extending to the left of switch 15 are of three different lengths as indicated by their numerical representation. For example, line E16B is 16 cells long and carries signals in the east direction, line E4B is four cells long going east, and line EB is one cell long going east. Line WB is one cell long going west.
Such a hierarchy of line lengths is shown in FIG. 3B, where line 34 is 16 cells long (only partly shown) going east, line 26 is four cells long going east, line 22 is one cell long going east and line 24 is one cell long going west. Switches 19 and 20 in the interior core of the user logic shown in FIG. 3B comprise a plurality of multiplexers each programmable by bits in the configuration memory 25 (see FIG. 1) to connect their input and output signals as desired by a user. This is discussed in more detail in PCT patent application publication number WO 94/10754 mentioned above.
FIG. 4 shows the internal structure of the pad driver 18 and the related switch of FIG. 3A. As shown in FIG. 4, switch 15 includes eight multiplexers 41 through 48, each for providing one of the output signals WB, W4B, W16B, WA, W4A, W16A, EN, and OUT. Input signals to these eight multiplexers are selected from the east-going input signals E16B, E4B, EB, E16A, F4A, EA, and the pad signal PADIN provided by pad driver 18.
Also shown in FIG. 4, pad driver 18 includes tristate output buffer 78 for providing output signal OUT to pad 16 under control of enable signal EN. The slew rate (switching speed) of output buffer 78 is also selectable by the user through memory cell SLEW. If pad driver 18 is configured to serve as an input driver, EN is set to make buffer 78 inactive. In the event that the chip is put into a package in which no pin 17 is connected, pullup control transistor TPUP is turned on by memory cell PUP to connect pullup resistor RPUP to the input terminal of input buffer 79 so the input voltage will not float to an intermediate state and drain power.
In FIG. 4, dashed lines are used to indicate configuration memory cells which control multiplexers and transistors in the switch and pad driver. The dashes suggest that the configuration memory cells are not visible in the picture. One can envision the memory cells as on a lower plane, as discussed above in connection with FIG. 1. In some cases, the memory cell is not directly connected to the multiplexer or transistor as shown, but is gated, for example through an AND gate which typically receives a global enable input. Signals from the memory cells which control the pullup transistor and slew rate on the output buffer are typically gated, and enable multiplexer 47 is typically controllable to provide a disabling output signal regardless of the values in its configuration memory cells. Such gating structures are not shown but are well known.
As illustrated in FIG. 1, the same pad driver circuit 18 shown in FIG. 4 is used for address and data pads which access configuration memory 25. For address pads, since the address lines are input only, the enable line EN is tied to ground and the OUT line is tied to either power or ground.